library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity arit_unit is
	port
	(
		a, b: in	std_logic_vector (7 downto 0);
		sel : in	std_logic_vector (2 downto 0);
		cin : in    std_logic;
		y	: out	std_logic_vector (7 downto 0)
	);
end arit_unit;

architecture arit_arch of arit_unit is
begin
with sel select
	y	<=	a			when	"000",
			a+1			when	"001",
			a-1			when	"010",
			b   		when    "011",
			b+1 		when    "100",
			b-1 		when    "101",
			a+b 		when    "110",
			(a+b)+cin 	when 	"111";
end arit_arch;